1. Field of the Invention
This invention relates to a method and apparatus for the characterization of surface and near-surface regions of a semiconductor substrate.
2. Description of the Relevant Art
Ion implantation is a process in which energetic, charged atoms or molecules are directly introduced into a semiconductor substrate. Ion implantation is primarily used to add dopant ions into the surfaces of semiconductor substrates. As semiconductor device dimensions shrink, ion implantation is steadily replacing chemical (diffusion) doping due primarily to the ability to more precisely control the doping process.
High-energy ion implantation, with acceleration energies measured in millions of electron volts (MeV), has shown the potential to reduce manufacturing costs of advanced complementary metal oxide semiconductor (CMOS) integrated circuits with minimum device dimensions of 0.5 .mu.m and smaller. High-energy ion implantation offers the potential use of impurity implants in relatively low-temperature gettering schemes, possibly allowing more expensive silicon epitaxial wafers to be replaced by less expensive Czochralski (CZ) bulk silicon wafers.
In high-energy ion implementation, impurities are driven into the substrate to depths of a few micrometers (microns). Localized damage to the crystalline lattice of a monolithic CZ silicon wafer during high-energy ion implantation may be recovered (annealed out) at relatively low temperatures.
High-energy ion implantation of oxygen atoms may replace the standard heat-cool-heat temperature cycling of CZ silicon wafers to produce intrinsic gettering sites. As a CZ silicon wafer is heated during an annealing process following oxygen ion implantation, oxygen clusters may grow into precipitates large enough to form desired lattice dislocations (gettering sites) in the wafer bulk at the implant depth. These gettering sites trap unwanted impurities which, if located in the active regions of devices near the surface of the wafer, would lower device performance and yield.
The formation of gettering sites just below the active regions of devices serves to increase their ability to trap unwanted impurities which might otherwise find their way into device active regions. Thus, under the right conditions, the use of high-energy ion implantation to place an implant layer in a CZ silicon wafer at a depth of a few microns may result in a "clean" and defect-free zone from the surface of the wafer to the implant depth. A semiconductor wafer with these characteristics is highly desirable for the manufacture of advanced integrated circuits with minimum device dimensions of 0.5 .mu.m and smaller.
Common techniques used to characterize implanted semiconductor substrates include secondary ion mass spectroscopy (SIMS), transmission electron microscopy (TEM), and various electrical tests. SIMS and TEM techniques are destructive in nature, and are relatively expensive in terms of time and materials expended. Electrical tests require test structures to be constructed on wafer surfaces, and are thus also relatively expensive in terms of time and materials.
More modern surface photovoltage (SPV) techniques to characterize implanted semiconductor substrates are nondestructive, require no special test structures, and may be performed relatively quickly. SPV techniques for detecting the presence of heavy metal contaminants in semiconductor substrates are well known. In brief, a train of monochromatic light pulses is directed at a semiconductor surface. If the energy of the incident light (photons) is greater than the bandgap of the semiconductor material, E.sub.g, photons penetrating the semiconductor material are eventually absorbed, producing excess charge carriers (holes and electrons) within the semiconductor substrate. These excess charge carriers diffuse to the surface of the semiconductor substrate, where they become separated by the electric field of the surface space charge region and produce a surface photovoltage. Knowing the photon flux and the absorption coefficient, the (average) minority carrier diffusion length may then be determined. U.S. Pat. No. 4,567,431; U.S. Pat. No. 5,025,145 (herein incorporated by reference). Heavy metal contaminants are known to reduce minority carrier diffusion lengths. Lagowski, et al., "Non-Contact Mapping of Heavy Metal Contamination for Silicon IC Fabrication," IOP Publishing, Ltd. 1992, pp. A185-A192 (herein incorporated by reference).
FIG. 1 shows a block diagram of an SPV test apparatus 100 for determining the minority carrier diffusion length in a semiconductor substrate 102 based on the relationship between incident photon flux and resulting surface photovoltage. Light source 104 includes an illumination source 106 and a rotating chopper 108. Light source 104 also includes an illumination attenuator and a set of filters for wavelength selection (not shown).
Rotating chopper 108 of light source 104 modulates a beam of monochromatic light 110 produced by illumination source 106. Light source 104 thus produces a train of monochromatic light pulses 112 with constant photon flux at each available wavelength. The train of monochromatic light pulses 112 passes through a housing 114 and strikes the surface of semiconductor substrate 102 resting on electrically grounded base plate 116. Pickup electrode 118 sends an electrical signal reflecting the level of the surface photovoltage of semiconductor substrate 102 to lock-in amplifier 120. Lock-in amplifier 120 is synchronized with rotating chopper 108 of light source 104 via an electrical signal from light source 104. Lock-in amplifier 120 provides an output signal reflecting the resultant level of surface photovoltage produced by semiconductor substrate 102 to data processor 122. Data processor 122 processes the input surface photovoltages produced at several different photon energy levels (i.e., wavelengths of incident light) to determine the minority carrier diffusion length in semiconductor substrate 102.
FIG. 2 shows that photons of the train of monochromatic light pulses 112 penetrate into semiconductor substrate 102 before absorption takes place. Typical SPV test apparatus use wavelengths of incident light which penetrate silicon semiconductor wafers to depths of from 10 .mu.m to 150 .mu.m.
FIG. 3 illustrates graphically how SPV test techniques work. The beam of monochromatic light 110 with constant photon flux .phi. is modulated by rotating chopper 108 of light source 104 to produce a train of monochromatic light pulses 112. The train of monochromatic light pulses 112 has an associated modulation period `T` and modulation frequency `f`, where f=1/T, and modulation frequency `f` of the train of monochromatic light pulses 112 is not related to the wavelength or frequency of the beam of monochromatic light 110.
More modern SPV techniques advocate fixed light beam modulation frequencies in the 500-600 Hz range in order to suppress hysteresis effects caused by trapping of minority carriers by deep levels and by surface states. Earlier SPV techniques used a fixed modulation frequency of about 10 Hz. See J. Lagowski, et al., "Non-Contact Mapping of Heavy Metal Contamination for Silicon IC Fabrication," IOP Publishing Ltd., 1992, pp. A185-A192 (herein incorporated by reference).
If the energy of the incident light (photons) is greater than the bandgap of the semiconductor material, E.sub.g, photons penetrating the semiconductor material are eventually absorbed, producing excess charge carriers (holes and electrons) within the semiconductor substrate. These excess charge carriers diffuse to the surface of the semiconductor substrate, where they become separated by the electric field of the surface space charge region and produce a surface photovoltage. In a semiconductor substrate doped with p-type material, surface photovoltage increases when an incident light pulse strikes the surface of the semiconductor substrate, and decreases when the light is blocked by rotating chopper 108 of light source 104. In a semiconductor substrate doped with n-type material, surface photovoltage decreases when an incident light pulse strikes the surface of the semiconductor substrate, and increases when the light is blocked by rotating chopper 108 of light source 104. Note that the number of excess charge carriers and the surface photovoltage would reach an equilibrium condition under continuous incident photon flux.
The monolithic crystalline lattice structure of a semiconductor substrate may develop a defect during the manufacture of the substrate or during subsequent device fabrication steps. As used herein, the term defect refers to any non-uniform material or structure present within a monolithic crystalline substrate which may negatively impact device performance. Among the most important device and substrate properties relevant to CMOS devices and influenced by crystalline defects include leakage currents in p-n junctions, minority carrier lifetimes, gate-oxide quality, and threshold voltage uniformity.
Material or structural defects may be present in the initial substrate starting material, or may be introduced into the substrate during fabrication of the substrate or during device fabrication processing steps. Exemplary defect materials include electrically active metal contaminants such as copper (Cu) and iron (Fe). Structural defects include point defects such as vacancies, line defects such as dislocation loops, and area defects such as stacking faults.
Structural defects are created within semiconductor substrates during ion implantation. An annealing process following ion implantation may not repair all of the damage caused to the crystalline lattice. Other device fabrication steps may also introduce material or structural defects which may lower device performance and yield. Thus it is important to be able to detect the presence of defects at any step in the device fabrication process.
FIG. 4 shows a semiconductor substrate 402, in which an implant layer 404 has been formed at a depth of 1 .mu.m using high-energy (MeV) ion implantation, undergoing an SPV test procedure. The train of monochromatic light pulses 112 of a typical SPV test apparatus penetrates silicon semiconductor wafers to depths of from 10 .mu.m to 150 .mu.m as shown. One of the problems with using conventional SPV test methods to determine the average minority carrier diffusion length of a semiconductor substrate 402 is that any defects at the implant depth caused by ion implantation may create recombination centers. These recombination centers may prevent many minority charge carriers produced below the implant layer from reaching the surface of the semiconductor substrate and producing a surface photovoltage.
A non-contact, non-destructive test method would allow substrates to be tested for defects before and after each step in a device fabrication process. Such a method would also allow sources of defects to be determined. Additionally, the relative success of an annealing process in repairing structural defects caused by ion implantation could be determined. It would further be advantageous to provide a method for characterizing the surface and near-surface regions of as-processed semiconductor substrates subjected to high-energy ion implantation using the advantages of SPV techniques, but without having to incur the burdensome disadvantages associated with the determination of minority carrier diffusion length. The problems of plotting the reciprocal of the induced photon flux surface photovoltage versus the reciprocal of the absorption coefficient, determining and rejecting non-linear points, and extrapolating along a straight line to determine minority carrier diffusion length would thus be avoided, potentially making the method more efficient and rapid.
Surface charge imaging (SCI) is a technique which uses SPV methods and high photon excitation levels. Under high photon excitation, energy bands become almost flat at the surface of a semiconductor wafer under test. Surface charge is then derived from measured surface photovoltage using an accepted equation described by P. Edelman, et al., "Surface Charge Imaging in Semiconductor Wafers by Surface Photovoltage (SPV)," Proceedings of the Materials Research Society Meeting, San Francisco, Calif., April, 1992 (incorporated herein by reference).
The P. Edelman et al. article describes an SCI technique which uses high-intensity laser light to map areas of varying surface charge on a semiconductor substrate. A fixed light modulation frequency of about 1.0 kHz is used in order to minimize interface state trapping. The technique is non-contact, non-destructive, and does not require the determination of minority carrier diffusion length, but was developed for a single purpose and does not allow for full characterization of the surface and near-surface region of as-processed semiconductor substrates.